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Job Description:
Developing and Implementing Verification Plans - Building Testbenches using Universal Verification Methodology(UVM) - Writing Test cases with both constrained-random and directed test cases to thoroughly exercise the design - Analyzing Simulation Results to identify and debug functional failures, working closely with design engineers - Debugging; identifying and resolving functional failures in the design, often in collaboration with design team - Collaborating with Teams: working with design, Cmodel and GC-level DV to ensure design quality and efficient verification closure
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